1. Field of the Invention
The present invention generally relates to content addressable memories and more particularly to an improved content addressable memory (CAM) that utilizes a single pair of lines as both the global bitlines and the search lines.
2. Description of the Related Art
Generally, CAM arrays have four vertical wires in each column. These are the true and complement bit lines and the true and complement search data lines. DRAM arrays accommodate fewer bits per bit line because of their low bit fine drive, which reduces the maximum column length of the array. This problem is remedied in conventional DRAM arrays by using global bit lines in the column direction to multiplex several banks of memory. However, in a DRAM CAM architecture, the use of global bit lines requires that each memory cell have six wires running over it in the column direction. This can become the pitch limiting factor of the array. The invention described herein provides the addition of global bit lines to a DRAM-based CAM array with no additional area penalty within the array core.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional content addressable memories the present invention has been devised, and it is an object of the present invention to provide a structure and method for improved content addressable memories.
In order to attain the object(s) suggested above, there is provided, according to a preferred aspect of the invention a dynamic random access memory content addressable memory (DCAM) array having a plurality of CAM cells. Each of the CAM cells has storage elements, transistors connected to the storage elements, a wordline connected to and controlling the transistors, bitlines connected to the storage devices through the transistors, and combined search and global bitlines connected to the storage elements. The cells are arranged in columns, each of which also contains multiplexers connected to the combined search and global bitlines, data-in lines connected to the multiplexers, and search-data lines connected to the multiplexers. Further, the multiplexers select between the data-in lines and the search-data lines to allow the combined search and global bitlines to be alternatively used as data lines and search lines.
Preferably, one or more drivers are provided between the multiplexers and the combined search and global bitlines. The driver drives a signal between the multiplexer and the combined search and global bitlines during search and write operations.
As mentioned above, it is desirable to utilize global bitlines in DRAM CAM arrays; However, the use of global bitlines requires a large number of wires, which limits the pitch of the array. The invention directly addresses this issue by utilizing currently available wires (search lines) 33, 34 as the global bitlines, thereby providing global bitlines without requiring any additional physical lines or area penalty within the array core.